Intel’s Jim Keller (helped design AMD K8 and Zen, now back at Intel) outlined scaling up to roughly 50x. Some articles talk about "gate density" increases, but it appears to be more about stacking:

Keller also said that intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. he claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with intel’s 10 nanometer generation of technology. "that’s basically already working," he said.
— jim keller

from wired via soylentnews